Guide to the basic architectures of a central processing unit (CPU)


The two essential basic architectures for CPUs are the Von Neumann and Harvard architecture.

In the Von Neumann architecture, named after the mathematician John von Neumann, there is no separation between the memory for data and program code.

In contrast, in the Harvard architecture, data and program (s) is stored in strictly separated storage and address spaces, on which it is typically accessed by means of two separated parallel bus systems.

Both architectures have their specific advantages and disadvantages. The Von Neumann architecture is simpler, since program code and data will be treated the same. This is consistent operating system routines for loading and saving usable.

Also, the program code as opposed to the Harvard architecture is able to modify itself, so machine code is easily modifiable via the debugger.

The separation into two physical memory and buses of the Harvard architecture results in better performance because data and program memory can be accessed in parallel. However, race conditions must be ruled out in such concurrent accesses that can lead to a non- deterministic program behavior.

In a Harvard architecture the physical separation of data and program form simple access rights which makes separation and memory protection feasible.

In order to prevent, for example, that software problems with program code can be overridden, there is a read-only operation in memory (eg, ROM, punch cards) used for the data.

It is not uncommon that a CPU has several independent data paths (particularly the L1 cache) and hierarchical levels in order to achieve a high output with as many parallel data paths.

The resulting risk of possible data inconsistencies and access race conditions can be prevented by consuming internal data protocols and management.

Instruction set of a Central processing unit (CPU)

The instruction set is the set of machine instructions of a processor. The scope of the instruction set varies considerably depending on the processor type.

Based on the size of the instruction set, processors can be distinguished between CISC (Complex Instruction Set Computing) – Calculating with complex instruction set and RISC processor architectures (Reduced Instruction Set Computing).

The traditional CISC architecture tries to handle more complex functions directly through machine instructions. It is characterized by the large number of available machine instructions exceeds 100.

They are also able to perform complex operations directly (about floating-point operations). This allows complex operations through a few powerful commands. The coexistence of complex (long) and simple (fast executable) commands makes an efficient processor design difficult, especially the pipeline design.

The RISC concept was created in the 1980s, in response, with the conscious renunciation of providing complex functionality in the form of instructions.

It attempts to provide very fast to be executed commands, but for only a few (less than 100), very simple commands. This results in the processor design significantly simplified and makes optimizations possible which usually allowed a higher CPU speed and faster execution speed.

This is due inter alia to the fact that less clock cycles are required due to lower the complexity (the decoding is faster). However, a simpler processor design means a shift of development effort to software as a provider of more complex functionality.

The compiler now has the task of efficient and correct implementation of the simplified instruction set.

Today, the x86 architecture is widely used – a typical representative of the CISC class – internally actually a RISC architecture, which decomposes the complex instructions provided in simple, RISC -like μ – code.

Another type of processor designs involves the use of the VLIW . There are several instructions that are summarized in one word. This is defined from the beginning, on which unit which instruction is running.

In addition, it also differs with the number of addresses in the machine instruction:

0 – address commands (stack machine)
1- address commands
2- address commands (typically CISC computer )
3- address commands (typically RISC machines )

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