Guide to the command processing of a central processing unit (CPU)


In principle, the command processing of a processor core follows the von Neumann cycle.

” FETCH ” : the address of the next machine instruction is read from the instruction address register. This is (more precisely, from the L1 cache) loaded from memory into the instruction register.

“Decode ” The command decoder decodes the command and activates corresponding circuits necessary for the execution of the command.
” FETCH operands” : Where to load additional data (required parameter), they are loaded from the L1 cache in the working register.

“EXECUTE” : The command is executed. This can be, for example operations in the arithmetic unit, a jump in (a change of command address register), writing back results into the main memory or the control of peripheral devices.

Depending on the output of some commands, the status register is set, which can be evaluated by subsequent commands.

“UPDATE instruction pointer”: If no branch instruction is to be performed in the EXECUTE stage, the instruction address register is then incremented by the length of the instruction, so that it points to the next machine instruction.

The hardware of a computer can make requests to the processor. Since these requests occur asynchronously, the processor is forced to regularly check if such requests exist, these may need to be emended before continuation of the actual program.


All programs are available as a sequence of binary machine instructions in memory. Only these commands can be processed. This code is almost impossible for a human to read.

For this reason, programs (such as BASIC, C , C + +, Java), are initially written in assembly language or a high-level language and then translated by a compiler into an executable file, that is, in machine language or run through an interpreter at runtime.

Symbolic machine instructions

To make it possible to write programs in a reasonable time, a symbolic notation for machine instructions was introduced (the assembly language). A keyword is assigned in assembly language to handle a machine instruction.

Since each processor has its own type of machine instructions, there is also a separate assembly language for it. Processor independent programming is possible only with the use of a high-level language, but the corresponding compiler is again processor specific.

Commands that are needed for each processor, are usually the same. The order of execution of assembler commands from the processor type, are shown in the following example:

MOV BX, $ 85F3 The value at address 85F3 ( hexadecimal notation ) is in the memory, it is loaded into the working register BX .
ADD BX, 15 The value of 15 is added to the contents of the working register BX .

Binary machine instructions

Machine instructions that are processor specific and consist of several parts. These include at least the actual command, the operation code (OP – CODE), the addressing mode, and the operand value or an address. They can be roughly divided into the following categories:

Arithmetic instructions
Logical commands
jump instructions
transport commands
Processor control commands

Command Processing

Most processors (including today’s microprocessors) essentially correspond to the Von Neumann architecture, and therefore the command processing follows broadly the Von Neumann cycle.

The main phases are loading (FETCH command), decoding (DECODE) and its execution (EXECUTE). Sometimes there is a distinction in the loading (operand fetch) and a write-back stage (WRITE BACK), in which the computational results are written to certain registers.

More complex microprocessors are interruptible, ie, an interruption of program execution can be effected by an external signal.

The software checks if an external event occurs (polling). These microprocessors come in extremely price sensitive sectors such as toys.

In addition to the parent command execution following the Von Neumann cycle, modern high performance processors dominate other techniques to speed up the program execution.

Modern high-performance microprocessors employ parallel techniques such as pipelining and superscalar, to allow any potential parallel execution of multiple commands, the individual steps of the command execution are slightly offset from each other.

Another way to run utilities is to accelerate the disorderly command execution (out-of-order execution), in which the commands will not be executed strictly according to the order specified by the program, but the processor attempts to individually optimize the order of commands.

The motivation for a deviation from the predefined command sequence is that branch instructions of the program can not always be safely predicted.

If you want to execute commands to a certain degree in parallel way, it is necessary in these cases to opt for a branch and execute the respective command sequence speculatively.

It is then possible that the other program command sequence must be executed so that the speculatively executed instructions must be reversed. In this sense, it known as a disordered command execution.

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