Central processing unit (CPU) – Understanding the data lines and caches


Buses (signal lines) connect the processor with other components.

Via the data bus data the memory is exchanged, as the information for the working register and the command register.

Depending on the processor architecture, a main processor (CPU) has a single bus for data memory (Von Neumann architecture) or several (usually two) separate data lines for the program code and normal data (Harvard architecture).

The address bus is used to transfer memory addresses. In each case a memory cell of the RAM is addressed (selected) in which – depending on the signal of the control bus – the data currently on the data bus is written.

Caches and MMU

Modern processors used in personal computers or other devices that require fast data processing, are equipped with caches. Caches are latches which latch the last processed data and commands and so allow rapid re-use.

They are the second level of the memory hierarchy. Nowadays, a processor has up to three-level cache:

Level 1 cache ( L1 cache): This cache runs at the processor clock. It is very small (about 4 to 256KB), but very quickly accessible due to its position in the processor core.

Level 2 cache (L2 cache) : The L2 cache is usually located in the processor, but not in the core itself It comprises between 64 kilobytes and 12 megabytes.

Level 3 cache (L3 cache) : For multi- core processors, the individual cores share the L3 cache. It is the slowest of the three caches, but also the largest (up to 256 megabytes).

The memory management unit (MMU) translates virtual addresses to real, simultaneously for all processor cores, and provides the cache coherence. Depending on their exact settlement of the cache levels, they can include either virtual or real addresses.

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